1. abstract rf amplifiers often experience impedance mismatch between output and load. such an impedance mismatch generates a reflected wave towards the rf power transistor, making a much more stringent working environment for the transistor. working conditions grow critical when the load is disconnected from the output of the rf power transistor, since, in this case, the reflected wave amplitude becomes comparable to the incident one. rf transistors are able to withstand severe impedance mismatch conditions particularly essential for applications such as plasma generators or nuclear magnetic resonators which operate under rough conditions. dmos devices used in such applications appeared to lack the necessary ruggness when operating under severe rf load mismatch conditions. such weakness was believed to be intrinsic. based on the need to improve the ruggedness of rf power dmos, an investigation was carried out and a theoretical model simulating the failure mode mechanism was developed. finally, relevant corrective actions were accordingly undertaken. 2. proposed model. figure 1: npn bipolar parasitic transistor under impedance mismatch conditions the rf power transistor is subjected to a reflected wave with an amplitude that cannot be controlled and, in the worse case, with a voltage value that can exceed the bvdss of the device itself. hence, the dmos works as a voltage clamp for this wave. under such conditions the device is subjected to an electric current whose amplitude is proportional to the power of the incident wave. simultaneously, the dmos experiences a temperature rise proportional to the july 2000 1/4 AN1232 application note ruggedness improvement of rf dmos devices a. grimaldi - a. schillaci - a. vitanza - e. romano
AN1232 - application note 2/4 duration, voltage swing (bvdss) and amplitude of the above current. in the dmos cross section, shown in figure 1, the presence of an npn bipolar parasitic transistor, in which the base and emitter are shorted by means of the dmos source metallization, are clearly noticed. under static conditions the parasitic transistor is inhibited by the short circuit, but under dynamic conditions, when the reverse breakdown current flows through the device, the short circuit condition itself is modified. in fact, this current crosses the base-emitter junction through the base resistance which is increased by the depletion layer due to the reverse voltage. this results in a variation in v be . we can assume that: v be =r be *i dis (*) if i dis (base distributed current) and r be (base distributed resistance) are large enough, the potential on the emitter side opposed to the short circuit is sufficient to turn-on the bipolar transistor, thus concentrating the current and destroying the device. a simplified model was developed (see figure 2) to simulate the mismatch condition on the drain of the dmos by means of the inductance l. figure 2: mismatch condition model during the turn off period the device is in breakdown condition and subjected to the current induced by the inductance, thus the device dissipates power. of course, depending on the turn off duration, we have to distinguish between the turn on of the parasitic transistor and the thermal derating, with relevant operations out of the reverse safe operating area of the dmos. in fact, during such operations it is possible that the device exceeds the maximum allowed junction temperature (200c). in the case of load mismatch, however, the value of the inductance is far from causing a thermal overstress. therefore, a turn on due to r be is far more likely to happen. another occurrence is when the voltage, due to the reflected wave, is applied on the drain of the dmos at zero current. in this case the capacitance of the body-drain junction is involved. this capacitance will suddenly change value due to the changed potential, hence making a current whose value is given by: i dis =c bd *dv/dt (**) gate voltage drain current drain voltage
AN1232 - application note 3/4 this together with (*) gives: v be =r be *c bd *dv/dt (***) therefore, one can see that even a zero current switching condition can cause the turn on of the parasitic transistor. 3. actions. in order to validate the model several tests were performed. the failure current was measured during an uis (unclamped inductive switching) test. in particular the failure current density was also tested. results are listed in table 1. in a typical dmos structure the body acts as the base of the parasitic transistor while the source behaves as the emitter. the rs pinched values are typically in the kws range. by using the existing diffusion processes it is not possible to change the body doping value in order to reduce either the dc gain (h fe ) or the r be . this would have a dramatic impact on the dmos threshold voltage. the only way to work on the parasitic transistor, without changing the characteristics of the dmos, is to add a further doping level called deep-body doping. by doing so the rs pinched is dramatically reduced to 100 ohm/square and the dc gain (hfe) of the parasitic transistor becomes close to one. this extra doping is implanted following the body doping process and prior to the body diffusion process. the dmos structure is therefore modified as shown in figure 3. figure 3: deep body doping since the deep body process is separated from the main body process (a further masking level and implant are required), typical dmos parameters are unaffected. optimum values for uis and in vswr can be obtained by using this structure and varying the deep body implant doses. results from the test performed on the sd2921 device are listed in table 1.
AN1232 - application note 4/4 table 1. 4. conclusion we have demonstrated that dmos ruggness, under varying load mismatches, is dramatically improved with a single implant process through photoresist without modifying the dmos layout. also, rf power performances remain unaffected. from now on, deep body doping process will be applied to all products in the production phase. vswr, a characteristic ruggedness parameter for rf power transistors, is linked to the standard ruggedness parameters of the dmos. therefore, a uis test, easily implemented and commonly applied in ews (electrical wafer sort), can give useful information on the ruggedness of rf power devices. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 2000 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com deep body dose uis failure (a) vswr none 10 5:1 1e15 26 15:1 2e15 39 20:1 3e15 45 30:1
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